Senior Design Verification Engineer

Senior / Principal Verification Engineer - Krakow

I am seeking a highly skilled

Verification Engineer

to join a cutting-edge team dedicated to hardware validation and electronic design automation (EDA). This role presents an exciting opportunity to work on advanced System-on-Chip (SoC) assembly and hardware / software interface (HSI) flows, influencing verification methodologies and development environments.

As a

Verification Engineer

, you will be responsible for defining, developing, and executing simulation-based verification tests to ensure the reliability and functionality of critical design tools. You will play a key role in enhancing continuous integration flows, automation, and validation methodologies.

Requirements & Skills

• Proven experience in 3+ sucessful tapeouts
• Strong expertise in

UVM

hardware RTL design languages

, including VHDL, Verilog, and SystemVerilog.

Python

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