Senior / Principal Verification Engineer

I am seeking a highly skilled

Senior / Principal Verification Engineer

to join a cutting-edge team dedicated to hardware validation and electronic design automation (EDA). This role presents an exciting opportunity to work on advanced System-on-Chip (SoC) assembly and hardware / software interface (HSI) flows, influencing verification methodologies and development environments.

As the

Senior / Principal Verification Engineer

, you will be responsible for defining, developing, and executing simulation-based verification tests to ensure the reliability and functionality of critical design tools. You will play a key role in enhancing continuous integration flows, automation, and validation methodologies.

Requirements & Skills

• Proven experience in 3+ successful tapeouts
• Strong expertise in UVM
• Knowledge of hardware RTL design languages, including VHDL, Verilog, and SystemVerilog
• Proficiency in Python
• Fluent in English
• Masters in Electronic Engineering or a related field

For more information on this role or others then please contact Jordan Browne.