Hardware Engineer

Who We Are

MA Capital is a proprietary trading firm specializing in systematic and high-performing discretionary strategies across multiple asset classes. We leverage advanced technology, quantitative research, and sophisticated models to capitalize on opportunities in global markets. Our culture is built on innovation, efficiency, and transparency. We are committed to providing liquidity and supporting fair, efficient markets, while ensuring our traders and professionals have flexibility, tools, and continuous learning opportunities to succeed.

Position Overview

We are seeking a skilled mid to senior-level FPGA engineer for a 1-month contract to build a

SystemVerilog-based HLS wrapper using the ExaNIC FDK TCP offload framework. The engineer will

design adapter-agnostic interfaces, CDC / FIFO modules between 10G network and PCIe clock

domains, and host integration via the ExaNIC FDK driver and C API. Target latency is under 100 ns

with line-rate performance.

Key Responsibilities

• Integrate ExaNIC FDK TCP offload across ExaNIC adapters.
• Develop SystemVerilog HLS wrapper and card-agnostic interfaces.
• Bridge AXI4-Stream Avalon-ST protocols with robust flow control.
• Implement CDC / FIFO modules using Vivado macros between 10G and PCIe clocks.
• Use ExaNIC FDK driver and C API for host card data / control.
• Build testbench with SVA and functional coverage.
• Produce performance analysis and optimization report.

Required Qualifications

Big Plus

Technical Environment

Development Environment Access

Contract Details